`timescale 1ns / 1ps

module bf16_divider_tb;

    // Inputs and outputs for the DUT (Device Under Test)
    reg [15:0] a;
    reg [15:0] b;
    wire [15:0] quotient;

    // Instantiate the DUT
    bf16_divider uut (
        .a(a),
        .b(b),
        .quotient(quotient)
    );

    // Test cases
    initial begin
        // Initialize inputs
        a = 16'b0_01111_0000000000; // 1.0 (BF16 format)
        b = 16'b0_01111_0000000000; // 1.0 (BF16 format)
        #10; // Wait for 10 ns
        $display("Test 1: a = %b, b = %b, quotient = %b", a, b, quotient);

        a = 16'b0_10000_0000000000; // 2.0 (BF16 format)
        b = 16'b0_01111_0000000000; // 1.0 (BF16 format)
        #10;
        $display("Test 2: a = %b, b = %b, quotient = %b", a, b, quotient);

        a = 16'b0_10000_0000000000; // 2.0 (BF16 format)
        b = 16'b0_10000_0000000000; // 2.0 (BF16 format)
        #10;
        $display("Test 3: a = %b, b = %b, quotient = %b", a, b, quotient);

        a = 16'b1_01111_0000000000; // -1.0 (BF16 format)
        b = 16'b0_01111_0000000000; // 1.0 (BF16 format)
        #10;
        $display("Test 4: a = %b, b = %b, quotient = %b", a, b, quotient);

        a = 16'b0_01111_0000000000; // 1.0 (BF16 format)
        b = 16'b1_01111_0000000000; // -1.0 (BF16 format)
        #10;
        $display("Test 5: a = %b, b = %b, quotient = %b", a, b, quotient);

        a = 16'b0_01111_1000000000; // 1.5 (BF16 format)
        b = 16'b0_01111_0000000000; // 1.0 (BF16 format)
        #10;
        $display("Test 6: a = %b, b = %b, quotient = %b", a, b, quotient);

        // Add more test cases as needed
        #10;
        $finish; // End the simulation
    end

endmodule